1. Field of the Invention
The present invention relates to a switching mode power supply, and more particularly, the present invention relates to the power supply with low standby loss and a main power converter connected parallelly with an auxiliary power converter of the power supply.
2. Description of the Related Art
In the design of a switching mode power source, a system requires high switching efficiency, high power density, high reliability, low production cost and quick dynamic response to a loading. With the worldwide campaign for saving energy, all switching mode power sources are demanded to have low standby power wastage. In this regard, various international organizations including the International Energy Association (IEA), the United States and many European countries have proposed or are planning a set of related standards to limit the power consumed by an electronic product using a switching mode power source in a standby mode.
The standard recommended by IEA and European countries includes a power source with a labeled input rating of 75 W or less, the non-loaded loss should be smaller than 0.75 W after 1 Jan. 2003. However, it is believed that more stringent standard will be established for large power sources in the future.
Currently, some of the methods for reducing standby power consumption include the following: 1. Lowering the switching frequency of a converter in the standby mode—Because a large portion of the energy consumed in the standby mode is the switching of power device, lowering the switching frequency can effectively reduce switching waste and hence reduces power waste in the standby mode. However, if this method is deployed to save energy, audio-noise will appear when the switching frequency is lowered to 20 KHz or below. Thus, some manufacturers developing this type of energy-saving control chips have to deploy frequency jolting and peak current limitation techniques to weaken or reduce noise signals. In addition, the method of reducing the switching frequency is only applicable to a pulse width modulation (PWM) converter. 2. Switches being operated intermittently—Through controlling the voltage differential amplifying signal or directly controlling the output voltage, the converters can operate intermittently in the standby mode. With this setup, the switching frequency per unit time is lowered and hence the switching waste is reduced. However, the ripple wave of the output voltage in the standby mode is considerably large and acoustic frequency noise signal is more likely to appear. Moreover, this method can be applied to a PWM converter and a resonance converter only. 3. Operating using small-power switches—In general, the switching loss and driving loss is related to the parameters of parasitic capacitor in a power device. For example, a small-power switch has a smaller parasitic capacitance. Hence, using a small-power switch in the standby mode can reduce the switching loss and driving loss of a converter.
Although all the aforementioned methods can reduce power loss in the standby mode, they can hardly meet some of the more stringent requirements for reducing power loss in switching mode power sources with a larger output power. For example, Dell, a U.S. Corporation, demands a power loss of 1 W for a 150 W device, which means when the power source outputs 0.5 W to a loading, the input power cannot exceed 1 W. Besides, the power source needs to have high switching efficiency, high power density, high reliability, low production cost and quick dynamic response to a loading. For high power application, in order to meet the requirement for high switching efficiency and high power density, the power supply adapts two-stage structure including a front-end with PFC connected to a DC/DC converter. Therefore, the switching loss and the driving loss of the circuits will be enormously increased owing to increasingly number of semiconductor switching devices and specifications of voltage and current of the semiconductor switching devices. Moreover, control circuits had varied more complicated accompanying with complicated circuits to need more power consumption. The above-mentioned three parts occupy most of the standby loss.
Therefore, in view of the above-mentioned drawbacks of prior art, a new scheme can be provided to achieve high switching efficiency, low cost, fast dynamic response to a load and stringent demand of standby loss.